The present invention relates generally to the fabrication of semiconductor devices, and more particularly, to a structure and method for stacked wafer fabrication.
In the semiconductor industry, efforts to reduce the thickness of a semiconductor wafer are in progress to respond to the goals of reducing the thickness of semiconductor packages, increase the chip speed, and for high-density fabrication. In stacked wafer fabrication, two or more semiconductor wafers having integrated circuits formed therein are joined together. Thickness reduction is performed by so-called backside grinding of a semiconductor wafer on the surface opposite that containing pattern-formed circuitry. Because the thinned wafer tends to have insufficient strength and is more susceptible to deformation such as bending and/or warping, an encapsulating step is typically performed in which a surface of the wafer is encapsulated in a molding compound (e.g., thermocuring epoxy resin), prior to the wafer being separated into individual chip packages using a dicing process. These individual chip packages are then mounted onto a substrate, such as a printed circuit board (PCB).
Conventional stacked wafer processes, however are not without their drawbacks. At times, where the molding compound becomes undone or delaminated from the wafer to which it is attached to, the wafer may be subject to warpage. Wafer warpage is detrimental to the fabrication process and tend to decrease the overall process yield and may degrade the quality and reliability of the chip packages that are produced. Moreover, where molding delamination from the wafer has occurred, the edges of chips of the wafer may be more susceptible to cracking, chipping, and/or corrosive environmental influences during the subsequent dicing process and associated handling.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved method of stacked wafer fabrication that avoids the shortcomings of the conventional wafer bonding processes.